1. Field of the Invention
This invention relates to a structure and process for mounting a semiconductor chip, such as large scale integration ("LSI"), on a carrier substrate.
2. Brief Description of Related Technology
In recent years, the popularity of small-sized electronic appliances, such as camera-integrated video tape recorders ("VTRs") and portable telephone sets, has made size reduction of LSI devices desirable. As a result of these reduction desires, chip size or chip scale packages ("CSPs") and ball grid arrays ("BGAs") are being used to reduce the size of packages substantially to that of bare chips. Such CSPs and BGAs improve the characteristics of the electronic device while retaining many of their operating features, thus serving to protect semiconductor bare chips, such as LSIS, and facilitate testing thereof.
Ordinarily, the CSP/BGA assembly is connected to electrical conductors on a circuit board by use of a solder connection or the like. However, when the resulting structure is exposed to thermal cycling, the reliability of the solder connection between the circuit board and the CSP/BGA often becomes suspect. Recently, after a CSP/BGA assembly is mounted on a circuit board, the space between the CSP/BGA assembly and the circuit board is often now filled with a sealing resin (often referred to as underfill sealing) in order to relieve stresses caused by thermal cycling, thereby improving heat shock properties and enhancing the reliability of the structure.
However, since thermosetting resins are typically used as the underfill sealing material, in the event of a failure after the CSP/BGA assembly is mounted on the circuit board, it is very difficult to replace the CSP/BGA assembly without destroying or scrapping the structure in its entirety.
To that end, techniques for mounting a bare chip on a circuit board are accepted as substantially similar to the mounting of a CSP/BGA onto a circuit board. One such technique, disclosed in Japanese Patent Laid-Open No. 102343/93, involves a mounting process where a bare chip is fixed and connected to a circuit board by use of a photocurable adhesive, where, in event of failure, this bare chip is removed therefrom. However, this technique is limited to those instances where the circuit board includes a transparent substrate (e.g., glass) which permits exposure to light from the back side, and the resulting structure exhibits poor heat shock properties.
Japanese Laid-Open Patent Publication No. 69280/94 discloses a process where a bare chip is fixed and connected to a substrate by use of a resin capable of hardening at a predetermined temperature. In the event of failure, this bare chip is removed from the substrate by softening the resin at a temperature higher than the predetermined temperature. However, no specific resin is disclosed, and there is no disclosure about treating the resin which remains on the substrate. Thus, the disclosed process is at best incomplete.
As pointed out in Japanese Patent Laid-Open No. 77264/94, it is conventional to use a solvent to remove residual resin from the circuit board. However, swelling the resin with a solvent is a time-consuming process and the corrosive organic acid ordinarily used as the solvent may reduce the reliability of the circuit board. Instead, that disclosure speaks to a method for removing residual resin by irradiation with electromagnetic radiation.
Japanese Patent Laid-Open No. 251516/93 also discloses a mounting process using bisphenol A type epoxy resin (CV5183 or CV5183S; manufactured by Matsushita Electric Industrial Co., Ltd.). However, the removal process so disclosed does not consistently permit easy removal of the chip, the curing step is lengthy at elevated temperatures, and the process generally results in poor productivity.
Accordingly, it would be desirable to have a mounting structure for semiconductor devices which readily removable in the event a failure is found and a process for fabricating such a structure.